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1: #ifndef _ASM_X86_ACPI_H 2: #define _ASM_X86_ACPI_H 3: 4: /* 5: * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6: * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org> 7: * 8: * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9: * 10: * This program is free software; you can redistribute it and/or modify 11: * it under the terms of the GNU General Public License as published by 12: * the Free Software Foundation; either version 2 of the License, or 13: * (at your option) any later version. 14: * 15: * This program is distributed in the hope that it will be useful, 16: * but WITHOUT ANY WARRANTY; without even the implied warranty of 17: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18: * GNU General Public License for more details. 19: * 20: * You should have received a copy of the GNU General Public License 21: * along with this program; if not, write to the Free Software 22: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23: * 24: * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 25: */ 26: #include <acpi/pdc_intel.h> 27: 28: #include <asm/numa.h> 29: #include <asm/fixmap.h> 30: #include <asm/processor.h> 31: #include <asm/mmu.h> 32: #include <asm/mpspec.h> 33: #include <asm/realmode.h> 34: 35: #define COMPILER_DEPENDENT_INT64 long long 36: #define COMPILER_DEPENDENT_UINT64 unsigned long long 37: 38: /* 39: * Calling conventions: 40: * 41: * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) 42: * ACPI_EXTERNAL_XFACE - External ACPI interfaces 43: * ACPI_INTERNAL_XFACE - Internal ACPI interfaces 44: * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces 45: */ 46: #define ACPI_SYSTEM_XFACE 47: #define ACPI_EXTERNAL_XFACE 48: #define ACPI_INTERNAL_XFACE 49: #define ACPI_INTERNAL_VAR_XFACE 50: 51: /* Asm macros */ 52: 53: #define ACPI_FLUSH_CPU_CACHE() wbinvd() 54: 55: int __acpi_acquire_global_lock(unsigned int *lock); 56: int __acpi_release_global_lock(unsigned int *lock); 57: 58: #define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ 59: ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) 60: 61: #define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ 62: ((Acq) = __acpi_release_global_lock(&facs->global_lock)) 63: 64: /* 65: * Math helper asm macros 66: */ 67: #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ 68: asm("divl %2;" \ 69: : "=a"(q32), "=d"(r32) \ 70: : "r"(d32), \ 71: "0"(n_lo), "1"(n_hi)) 72: 73: 74: #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \ 75: asm("shrl $1,%2 ;" \ 76: "rcrl $1,%3;" \ 77: : "=r"(n_hi), "=r"(n_lo) \ 78: : "0"(n_hi), "1"(n_lo)) 79: 80: #ifdef CONFIG_ACPI 81: extern int acpi_lapic; 82: extern int acpi_ioapic; 83: extern int acpi_noirq; 84: extern int acpi_strict; 85: extern int acpi_disabled; 86: extern int acpi_pci_disabled; 87: extern int acpi_skip_timer_override; 88: extern int acpi_use_timer_override; 89: extern int acpi_fix_pin2_polarity; 90: extern int acpi_disable_cmcff; 91: 92: extern u8 acpi_sci_flags; 93: extern int acpi_sci_override_gsi; 94: void acpi_pic_sci_set_trigger(unsigned int, u16); 95: 96: extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi, 97: int trigger, int polarity); 98: 99: static inline void disable_acpi(void) 100: { 101: acpi_disabled = 1; 102: acpi_pci_disabled = 1; 103: acpi_noirq = 1; 104: } 105: 106: extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); 107: 108: static inline void acpi_noirq_set(void) { acpi_noirq = 1; } 109: static inline void acpi_disable_pci(void) 110: { 111: acpi_pci_disabled = 1; 112: acpi_noirq_set(); 113: } 114: 115: /* Low-level suspend routine. */ 116: extern int (*acpi_suspend_lowlevel)(void); 117: 118: /* Physical address to resume after wakeup */ 119: #define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start)) 120: 121: /* 122: * Check if the CPU can handle C2 and deeper 123: */ 124: static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) 125: { 126: /* 127: * Early models (<=5) of AMD Opterons are not supposed to go into 128: * C2 state. 129: * 130: * Steppings 0x0A and later are good 131: */ 132: if (boot_cpu_data.x86 == 0x0F && 133: boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 134: boot_cpu_data.x86_model <= 0x05 && 135: boot_cpu_data.x86_mask < 0x0A) 136: return 1; 137: else if (amd_e400_c1e_detected) 138: return 1; 139: else 140: return max_cstate; 141: } 142: 143: static inline bool arch_has_acpi_pdc(void) 144: { 145: struct cpuinfo_x86 *c = &cpu_data(0); 146: return (c->x86_vendor == X86_VENDOR_INTEL || 147: c->x86_vendor == X86_VENDOR_CENTAUR); 148: } 149: 150: static inline void arch_acpi_set_pdc_bits(u32 *buf) 151: { 152: struct cpuinfo_x86 *c = &cpu_data(0); 153: 154: buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; 155: 156: if (cpu_has(c, X86_FEATURE_EST)) 157: buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; 158: 159: if (cpu_has(c, X86_FEATURE_ACPI)) 160: buf[2] |= ACPI_PDC_T_FFH; 161: 162: /* 163: * If mwait/monitor is unsupported, C2/C3_FFH will be disabled 164: */ 165: if (!cpu_has(c, X86_FEATURE_MWAIT)) 166: buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); 167: } 168: 169: #else /* !CONFIG_ACPI */ 170: 171: #define acpi_lapic 0 172: #define acpi_ioapic 0 173: #define acpi_disable_cmcff 0 174: static inline void acpi_noirq_set(void) { } 175: static inline void acpi_disable_pci(void) { } 176: static inline void disable_acpi(void) { } 177: 178: #endif /* !CONFIG_ACPI */ 179: 180: #define ARCH_HAS_POWER_INIT 1 181: 182: #ifdef CONFIG_ACPI_NUMA 183: extern int acpi_numa; 184: extern int x86_acpi_numa_init(void); 185: #endif /* CONFIG_ACPI_NUMA */ 186: 187: #define acpi_unlazy_tlb(x) leave_mm(x) 188: 189: #endif /* _ASM_X86_ACPI_H */ 190: