Green shading in the line number column means the source is part of the translation unit, red means it is conditionally excluded. Highlighted line numbers link to the translation unit page. Highlighted macros link to the macro page.
1: #ifndef _ASM_X86_IO_APIC_H 2: #define _ASM_X86_IO_APIC_H 3: 4: #include <linux/types.h> 5: #include <asm/mpspec.h> 6: #include <asm/apicdef.h> 7: #include <asm/irq_vectors.h> 8: #include <asm/x86_init.h> 9: /* 10: * Intel IO-APIC support for SMP and UP systems. 11: * 12: * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 13: */ 14: 15: /* I/O Unit Redirection Table */ 16: #define IO_APIC_REDIR_VECTOR_MASK 0x000FF 17: #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 18: #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 19: #define IO_APIC_REDIR_SEND_PENDING (1 << 12) 20: #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) 21: #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) 22: #define IO_APIC_REDIR_MASKED (1 << 16) 23: 24: /* 25: * The structure of the IO-APIC: 26: */ 27: union IO_APIC_reg_00 { 28: u32 raw; 29: struct { 30: u32 __reserved_2 : 14, 31: LTS : 1, 32: delivery_type : 1, 33: __reserved_1 : 8, 34: ID : 8; 35: } __attribute__ ((packed)) bits; 36: }; 37: 38: union IO_APIC_reg_01 { 39: u32 raw; 40: struct { 41: u32 version : 8, 42: __reserved_2 : 7, 43: PRQ : 1, 44: entries : 8, 45: __reserved_1 : 8; 46: } __attribute__ ((packed)) bits; 47: }; 48: 49: union IO_APIC_reg_02 { 50: u32 raw; 51: struct { 52: u32 __reserved_2 : 24, 53: arbitration : 4, 54: __reserved_1 : 4; 55: } __attribute__ ((packed)) bits; 56: }; 57: 58: union IO_APIC_reg_03 { 59: u32 raw; 60: struct { 61: u32 boot_DT : 1, 62: __reserved_1 : 31; 63: } __attribute__ ((packed)) bits; 64: }; 65: 66: struct IO_APIC_route_entry { 67: __u32 vector : 8, 68: delivery_mode : 3, /* 000: FIXED 69: * 001: lowest prio 70: * 111: ExtINT 71: */ 72: dest_mode : 1, /* 0: physical, 1: logical */ 73: delivery_status : 1, 74: polarity : 1, 75: irr : 1, 76: trigger : 1, /* 0: edge, 1: level */ 77: mask : 1, /* 0: enabled, 1: disabled */ 78: __reserved_2 : 15; 79: 80: __u32 __reserved_3 : 24, 81: dest : 8; 82: } __attribute__ ((packed)); 83: 84: struct IR_IO_APIC_route_entry { 85: __u64 vector : 8, 86: zero : 3, 87: index2 : 1, 88: delivery_status : 1, 89: polarity : 1, 90: irr : 1, 91: trigger : 1, 92: mask : 1, 93: reserved : 31, 94: format : 1, 95: index : 15; 96: } __attribute__ ((packed)); 97: 98: #define IOAPIC_AUTO -1 99: #define IOAPIC_EDGE 0 100: #define IOAPIC_LEVEL 1 101: 102: #ifdef CONFIG_X86_IO_APIC 103: 104: /* 105: * # of IO-APICs and # of IRQ routing registers 106: */ 107: extern int nr_ioapics; 108: 109: extern int mpc_ioapic_id(int ioapic); 110: extern unsigned int mpc_ioapic_addr(int ioapic); 111: extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic); 112: 113: #define MP_MAX_IOAPIC_PIN 127 114: 115: /* # of MP IRQ source entries */ 116: extern int mp_irq_entries; 117: 118: /* MP IRQ source entries */ 119: extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 120: 121: /* non-0 if default (table-less) MP configuration */ 122: extern int mpc_default_type; 123: 124: /* Older SiS APIC requires we rewrite the index register */ 125: extern int sis_apic_bug; 126: 127: /* 1 if "noapic" boot option passed */ 128: extern int skip_ioapic_setup; 129: 130: /* 1 if "noapic" boot option passed */ 131: extern int noioapicquirk; 132: 133: /* -1 if "noapic" boot option passed */ 134: extern int noioapicreroute; 135: 136: /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ 137: extern int timer_through_8259; 138: 139: /* 140: * If we use the IO-APIC for IRQ routing, disable automatic 141: * assignment of PCI IRQ's. 142: */ 143: #define io_apic_assign_pci_irqs \ 144: (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) 145: 146: struct io_apic_irq_attr; 147: struct irq_cfg; 148: extern int io_apic_set_pci_routing(struct device *dev, int irq, 149: struct io_apic_irq_attr *irq_attr); 150: void setup_IO_APIC_irq_extra(u32 gsi); 151: extern void ioapic_insert_resources(void); 152: 153: extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, 154: unsigned int, int, 155: struct io_apic_irq_attr *); 156: extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, 157: unsigned int, int, 158: struct io_apic_irq_attr *); 159: extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); 160: 161: extern void native_compose_msi_msg(struct pci_dev *pdev, 162: unsigned int irq, unsigned int dest, 163: struct msi_msg *msg, u8 hpet_id); 164: extern void native_eoi_ioapic_pin(int apic, int pin, int vector); 165: int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr); 166: 167: extern int save_ioapic_entries(void); 168: extern void mask_ioapic_entries(void); 169: extern int restore_ioapic_entries(void); 170: 171: extern int get_nr_irqs_gsi(void); 172: 173: extern void setup_ioapic_ids_from_mpc(void); 174: extern void setup_ioapic_ids_from_mpc_nocheck(void); 175: 176: struct mp_ioapic_gsi{ 177: u32 gsi_base; 178: u32 gsi_end; 179: }; 180: extern struct mp_ioapic_gsi mp_gsi_routing[]; 181: extern u32 gsi_top; 182: int mp_find_ioapic(u32 gsi); 183: int mp_find_ioapic_pin(int ioapic, u32 gsi); 184: void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); 185: extern void __init pre_init_apic_IRQ0(void); 186: 187: extern void mp_save_irq(struct mpc_intsrc *m); 188: 189: extern void disable_ioapic_support(void); 190: 191: extern void __init native_io_apic_init_mappings(void); 192: extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); 193: extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val); 194: extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val); 195: extern void native_disable_io_apic(void); 196: extern void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries); 197: extern void intel_ir_io_apic_print_entries(unsigned int apic, unsigned int nr_entries); 198: extern int native_ioapic_set_affinity(struct irq_data *, 199: const struct cpumask *, 200: bool); 201: 202: static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) 203: { 204: return x86_io_apic_ops.read(apic, reg); 205: } 206: 207: static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) 208: { 209: x86_io_apic_ops.write(apic, reg, value); 210: } 211: static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) 212: { 213: x86_io_apic_ops.modify(apic, reg, value); 214: } 215: 216: extern void io_apic_eoi(unsigned int apic, unsigned int vector); 217: 218: #else /* !CONFIG_X86_IO_APIC */ 219: 220: #define io_apic_assign_pci_irqs 0 221: #define setup_ioapic_ids_from_mpc x86_init_noop 222: static const int timer_through_8259 = 0; 223: static inline void ioapic_insert_resources(void) { } 224: #define gsi_top (NR_IRQS_LEGACY) 225: static inline int mp_find_ioapic(u32 gsi) { return 0; } 226: 227: struct io_apic_irq_attr; 228: static inline int io_apic_set_pci_routing(struct device *dev, int irq, 229: struct io_apic_irq_attr *irq_attr) { return 0; } 230: 231: static inline int save_ioapic_entries(void) 232: { 233: return -ENOMEM; 234: } 235: 236: static inline void mask_ioapic_entries(void) { } 237: static inline int restore_ioapic_entries(void) 238: { 239: return -ENOMEM; 240: } 241: 242: static inline void mp_save_irq(struct mpc_intsrc *m) { }; 243: static inline void disable_ioapic_support(void) { } 244: #define native_io_apic_init_mappings NULL 245: #define native_io_apic_read NULL 246: #define native_io_apic_write NULL 247: #define native_io_apic_modify NULL 248: #define native_disable_io_apic NULL 249: #define native_io_apic_print_entries NULL 250: #define native_ioapic_set_affinity NULL 251: #define native_setup_ioapic_entry NULL 252: #define native_compose_msi_msg NULL 253: #define native_eoi_ioapic_pin NULL 254: #endif 255: 256: #endif /* _ASM_X86_IO_APIC_H */ 257: