Green shading in the line number column means the source is part of the translation unit, red means it is conditionally excluded. Highlighted line numbers link to the translation unit page. Highlighted macros link to the macro page.
1: #ifndef _ASM_X86_PERCPU_H 2: #define _ASM_X86_PERCPU_H 3: 4: #ifdef CONFIG_X86_64 5: #define __percpu_seg gs 6: #define __percpu_mov_op movq 7: #else 8: #define __percpu_seg fs 9: #define __percpu_mov_op movl 10: #endif 11: 12: #ifdef __ASSEMBLY__ 13: 14: /* 15: * PER_CPU finds an address of a per-cpu variable. 16: * 17: * Args: 18: * var - variable name 19: * reg - 32bit register 20: * 21: * The resulting address is stored in the "reg" argument. 22: * 23: * Example: 24: * PER_CPU(cpu_gdt_descr, %ebx) 25: */ 26: #ifdef CONFIG_SMP 27: #define PER_CPU(var, reg) \ 28: __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \ 29: lea var(reg), reg 30: #define PER_CPU_VAR(var) %__percpu_seg:var 31: #else /* ! SMP */ 32: #define PER_CPU(var, reg) __percpu_mov_op $var, reg 33: #define PER_CPU_VAR(var) var 34: #endif /* SMP */ 35: 36: #ifdef CONFIG_X86_64_SMP 37: #define INIT_PER_CPU_VAR(var) init_per_cpu__##var 38: #else 39: #define INIT_PER_CPU_VAR(var) var 40: #endif 41: 42: #else /* ...!ASSEMBLY */ 43: 44: #include <linux/kernel.h> 45: #include <linux/stringify.h> 46: 47: #ifdef CONFIG_SMP 48: #define __percpu_prefix "%%"__stringify(__percpu_seg)":" 49: #define __my_cpu_offset this_cpu_read(this_cpu_off) 50: 51: /* 52: * Compared to the generic __my_cpu_offset version, the following 53: * saves one instruction and avoids clobbering a temp register. 54: */ 55: #define __this_cpu_ptr(ptr) \ 56: ({ \ 57: unsigned long tcp_ptr__; \ 58: __verify_pcpu_ptr(ptr); \ 59: asm volatile("add " __percpu_arg(1) ", %0" \ 60: : "=r" (tcp_ptr__) \ 61: : "m" (this_cpu_off), "0" (ptr)); \ 62: (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ 63: }) 64: #else 65: #define __percpu_prefix "" 66: #endif 67: 68: #define __percpu_arg(x) __percpu_prefix "%P" #x 69: 70: /* 71: * Initialized pointers to per-cpu variables needed for the boot 72: * processor need to use these macros to get the proper address 73: * offset from __per_cpu_load on SMP. 74: * 75: * There also must be an entry in vmlinux_64.lds.S 76: */ 77: #define DECLARE_INIT_PER_CPU(var) \ 78: extern typeof(var) init_per_cpu_var(var) 79: 80: #ifdef CONFIG_X86_64_SMP 81: #define init_per_cpu_var(var) init_per_cpu__##var 82: #else 83: #define init_per_cpu_var(var) var 84: #endif 85: 86: /* For arch-specific code, we can use direct single-insn ops (they 87: * don't give an lvalue though). */ 88: extern void __bad_percpu_size(void); 89: 90: #define percpu_to_op(op, var, val) \ 91: do { \ 92: typedef typeof(var) pto_T__; \ 93: if (0) { \ 94: pto_T__ pto_tmp__; \ 95: pto_tmp__ = (val); \ 96: (void)pto_tmp__; \ 97: } \ 98: switch (sizeof(var)) { \ 99: case 1: \ 100: asm(op "b %1,"__percpu_arg(0) \ 101: : "+m" (var) \ 102: : "qi" ((pto_T__)(val))); \ 103: break; \ 104: case 2: \ 105: asm(op "w %1,"__percpu_arg(0) \ 106: : "+m" (var) \ 107: : "ri" ((pto_T__)(val))); \ 108: break; \ 109: case 4: \ 110: asm(op "l %1,"__percpu_arg(0) \ 111: : "+m" (var) \ 112: : "ri" ((pto_T__)(val))); \ 113: break; \ 114: case 8: \ 115: asm(op "q %1,"__percpu_arg(0) \ 116: : "+m" (var) \ 117: : "re" ((pto_T__)(val))); \ 118: break; \ 119: default: __bad_percpu_size(); \ 120: } \ 121: } while (0) 122: 123: /* 124: * Generate a percpu add to memory instruction and optimize code 125: * if one is added or subtracted. 126: */ 127: #define percpu_add_op(var, val) \ 128: do { \ 129: typedef typeof(var) pao_T__; \ 130: const int pao_ID__ = (__builtin_constant_p(val) && \ 131: ((val) == 1 || (val) == -1)) ? \ 132: (int)(val) : 0; \ 133: if (0) { \ 134: pao_T__ pao_tmp__; \ 135: pao_tmp__ = (val); \ 136: (void)pao_tmp__; \ 137: } \ 138: switch (sizeof(var)) { \ 139: case 1: \ 140: if (pao_ID__ == 1) \ 141: asm("incb "__percpu_arg(0) : "+m" (var)); \ 142: else if (pao_ID__ == -1) \ 143: asm("decb "__percpu_arg(0) : "+m" (var)); \ 144: else \ 145: asm("addb %1, "__percpu_arg(0) \ 146: : "+m" (var) \ 147: : "qi" ((pao_T__)(val))); \ 148: break; \ 149: case 2: \ 150: if (pao_ID__ == 1) \ 151: asm("incw "__percpu_arg(0) : "+m" (var)); \ 152: else if (pao_ID__ == -1) \ 153: asm("decw "__percpu_arg(0) : "+m" (var)); \ 154: else \ 155: asm("addw %1, "__percpu_arg(0) \ 156: : "+m" (var) \ 157: : "ri" ((pao_T__)(val))); \ 158: break; \ 159: case 4: \ 160: if (pao_ID__ == 1) \ 161: asm("incl "__percpu_arg(0) : "+m" (var)); \ 162: else if (pao_ID__ == -1) \ 163: asm("decl "__percpu_arg(0) : "+m" (var)); \ 164: else \ 165: asm("addl %1, "__percpu_arg(0) \ 166: : "+m" (var) \ 167: : "ri" ((pao_T__)(val))); \ 168: break; \ 169: case 8: \ 170: if (pao_ID__ == 1) \ 171: asm("incq "__percpu_arg(0) : "+m" (var)); \ 172: else if (pao_ID__ == -1) \ 173: asm("decq "__percpu_arg(0) : "+m" (var)); \ 174: else \ 175: asm("addq %1, "__percpu_arg(0) \ 176: : "+m" (var) \ 177: : "re" ((pao_T__)(val))); \ 178: break; \ 179: default: __bad_percpu_size(); \ 180: } \ 181: } while (0) 182: 183: #define percpu_from_op(op, var, constraint) \ 184: ({ \ 185: typeof(var) pfo_ret__; \ 186: switch (sizeof(var)) { \ 187: case 1: \ 188: asm(op "b "__percpu_arg(1)",%0" \ 189: : "=q" (pfo_ret__) \ 190: : constraint); \ 191: break; \ 192: case 2: \ 193: asm(op "w "__percpu_arg(1)",%0" \ 194: : "=r" (pfo_ret__) \ 195: : constraint); \ 196: break; \ 197: case 4: \ 198: asm(op "l "__percpu_arg(1)",%0" \ 199: : "=r" (pfo_ret__) \ 200: : constraint); \ 201: break; \ 202: case 8: \ 203: asm(op "q "__percpu_arg(1)",%0" \ 204: : "=r" (pfo_ret__) \ 205: : constraint); \ 206: break; \ 207: default: __bad_percpu_size(); \ 208: } \ 209: pfo_ret__; \ 210: }) 211: 212: #define percpu_unary_op(op, var) \ 213: ({ \ 214: switch (sizeof(var)) { \ 215: case 1: \ 216: asm(op "b "__percpu_arg(0) \ 217: : "+m" (var)); \ 218: break; \ 219: case 2: \ 220: asm(op "w "__percpu_arg(0) \ 221: : "+m" (var)); \ 222: break; \ 223: case 4: \ 224: asm(op "l "__percpu_arg(0) \ 225: : "+m" (var)); \ 226: break; \ 227: case 8: \ 228: asm(op "q "__percpu_arg(0) \ 229: : "+m" (var)); \ 230: break; \ 231: default: __bad_percpu_size(); \ 232: } \ 233: }) 234: 235: /* 236: * Add return operation 237: */ 238: #define percpu_add_return_op(var, val) \ 239: ({ \ 240: typeof(var) paro_ret__ = val; \ 241: switch (sizeof(var)) { \ 242: case 1: \ 243: asm("xaddb %0, "__percpu_arg(1) \ 244: : "+q" (paro_ret__), "+m" (var) \ 245: : : "memory"); \ 246: break; \ 247: case 2: \ 248: asm("xaddw %0, "__percpu_arg(1) \ 249: : "+r" (paro_ret__), "+m" (var) \ 250: : : "memory"); \ 251: break; \ 252: case 4: \ 253: asm("xaddl %0, "__percpu_arg(1) \ 254: : "+r" (paro_ret__), "+m" (var) \ 255: : : "memory"); \ 256: break; \ 257: case 8: \ 258: asm("xaddq %0, "__percpu_arg(1) \ 259: : "+re" (paro_ret__), "+m" (var) \ 260: : : "memory"); \ 261: break; \ 262: default: __bad_percpu_size(); \ 263: } \ 264: paro_ret__ += val; \ 265: paro_ret__; \ 266: }) 267: 268: /* 269: * xchg is implemented using cmpxchg without a lock prefix. xchg is 270: * expensive due to the implied lock prefix. The processor cannot prefetch 271: * cachelines if xchg is used. 272: */ 273: #define percpu_xchg_op(var, nval) \ 274: ({ \ 275: typeof(var) pxo_ret__; \ 276: typeof(var) pxo_new__ = (nval); \ 277: switch (sizeof(var)) { \ 278: case 1: \ 279: asm("\n\tmov "__percpu_arg(1)",%%al" \ 280: "\n1:\tcmpxchgb %2, "__percpu_arg(1) \ 281: "\n\tjnz 1b" \ 282: : "=&a" (pxo_ret__), "+m" (var) \ 283: : "q" (pxo_new__) \ 284: : "memory"); \ 285: break; \ 286: case 2: \ 287: asm("\n\tmov "__percpu_arg(1)",%%ax" \ 288: "\n1:\tcmpxchgw %2, "__percpu_arg(1) \ 289: "\n\tjnz 1b" \ 290: : "=&a" (pxo_ret__), "+m" (var) \ 291: : "r" (pxo_new__) \ 292: : "memory"); \ 293: break; \ 294: case 4: \ 295: asm("\n\tmov "__percpu_arg(1)",%%eax" \ 296: "\n1:\tcmpxchgl %2, "__percpu_arg(1) \ 297: "\n\tjnz 1b" \ 298: : "=&a" (pxo_ret__), "+m" (var) \ 299: : "r" (pxo_new__) \ 300: : "memory"); \ 301: break; \ 302: case 8: \ 303: asm("\n\tmov "__percpu_arg(1)",%%rax" \ 304: "\n1:\tcmpxchgq %2, "__percpu_arg(1) \ 305: "\n\tjnz 1b" \ 306: : "=&a" (pxo_ret__), "+m" (var) \ 307: : "r" (pxo_new__) \ 308: : "memory"); \ 309: break; \ 310: default: __bad_percpu_size(); \ 311: } \ 312: pxo_ret__; \ 313: }) 314: 315: /* 316: * cmpxchg has no such implied lock semantics as a result it is much 317: * more efficient for cpu local operations. 318: */ 319: #define percpu_cmpxchg_op(var, oval, nval) \ 320: ({ \ 321: typeof(var) pco_ret__; \ 322: typeof(var) pco_old__ = (oval); \ 323: typeof(var) pco_new__ = (nval); \ 324: switch (sizeof(var)) { \ 325: case 1: \ 326: asm("cmpxchgb %2, "__percpu_arg(1) \ 327: : "=a" (pco_ret__), "+m" (var) \ 328: : "q" (pco_new__), "0" (pco_old__) \ 329: : "memory"); \ 330: break; \ 331: case 2: \ 332: asm("cmpxchgw %2, "__percpu_arg(1) \ 333: : "=a" (pco_ret__), "+m" (var) \ 334: : "r" (pco_new__), "0" (pco_old__) \ 335: : "memory"); \ 336: break; \ 337: case 4: \ 338: asm("cmpxchgl %2, "__percpu_arg(1) \ 339: : "=a" (pco_ret__), "+m" (var) \ 340: : "r" (pco_new__), "0" (pco_old__) \ 341: : "memory"); \ 342: break; \ 343: case 8: \ 344: asm("cmpxchgq %2, "__percpu_arg(1) \ 345: : "=a" (pco_ret__), "+m" (var) \ 346: : "r" (pco_new__), "0" (pco_old__) \ 347: : "memory"); \ 348: break; \ 349: default: __bad_percpu_size(); \ 350: } \ 351: pco_ret__; \ 352: }) 353: 354: /* 355: * this_cpu_read() makes gcc load the percpu variable every time it is 356: * accessed while this_cpu_read_stable() allows the value to be cached. 357: * this_cpu_read_stable() is more efficient and can be used if its value 358: * is guaranteed to be valid across cpus. The current users include 359: * get_current() and get_thread_info() both of which are actually 360: * per-thread variables implemented as per-cpu variables and thus 361: * stable for the duration of the respective task. 362: */ 363: #define this_cpu_read_stable(var) percpu_from_op("mov", var, "p" (&(var))) 364: 365: #define __this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 366: #define __this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 367: #define __this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 368: 369: #define __this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 370: #define __this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 371: #define __this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 372: #define __this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 373: #define __this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 374: #define __this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 375: #define __this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 376: #define __this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 377: #define __this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 378: #define __this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 379: #define __this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 380: #define __this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 381: #define __this_cpu_xchg_1(pcp, val) percpu_xchg_op(pcp, val) 382: #define __this_cpu_xchg_2(pcp, val) percpu_xchg_op(pcp, val) 383: #define __this_cpu_xchg_4(pcp, val) percpu_xchg_op(pcp, val) 384: 385: #define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 386: #define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 387: #define this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 388: #define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 389: #define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 390: #define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 391: #define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 392: #define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 393: #define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 394: #define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 395: #define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 396: #define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 397: #define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 398: #define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 399: #define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 400: #define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) 401: #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) 402: #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) 403: 404: #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 405: #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 406: #define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 407: #define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 408: #define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 409: #define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 410: 411: #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 412: #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 413: #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 414: #define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 415: #define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 416: #define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 417: 418: #ifdef CONFIG_X86_CMPXCHG64 419: #define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2) \ 420: ({ \ 421: bool __ret; \ 422: typeof(pcp1) __o1 = (o1), __n1 = (n1); \ 423: typeof(pcp2) __o2 = (o2), __n2 = (n2); \ 424: asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \ 425: : "=a" (__ret), "+m" (pcp1), "+m" (pcp2), "+d" (__o2) \ 426: : "b" (__n1), "c" (__n2), "a" (__o1)); \ 427: __ret; \ 428: }) 429: 430: #define __this_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double 431: #define this_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double 432: #endif /* CONFIG_X86_CMPXCHG64 */ 433: 434: /* 435: * Per cpu atomic 64 bit operations are only available under 64 bit. 436: * 32 bit must fall back to generic operations. 437: */ 438: #ifdef CONFIG_X86_64 439: #define __this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 440: #define __this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 441: #define __this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 442: #define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 443: #define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 444: #define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 445: #define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 446: #define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 447: 448: #define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 449: #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 450: #define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 451: #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 452: #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 453: #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 454: #define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 455: #define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 456: 457: /* 458: * Pretty complex macro to generate cmpxchg16 instruction. The instruction 459: * is not supported on early AMD64 processors so we must be able to emulate 460: * it in software. The address used in the cmpxchg16 instruction must be 461: * aligned to a 16 byte boundary. 462: */ 463: #define percpu_cmpxchg16b_double(pcp1, pcp2, o1, o2, n1, n2) \ 464: ({ \ 465: bool __ret; \ 466: typeof(pcp1) __o1 = (o1), __n1 = (n1); \ 467: typeof(pcp2) __o2 = (o2), __n2 = (n2); \ 468: alternative_io("leaq %P1,%%rsi\n\tcall this_cpu_cmpxchg16b_emu\n\t", \ 469: "cmpxchg16b " __percpu_arg(1) "\n\tsetz %0\n\t", \ 470: X86_FEATURE_CX16, \ 471: ASM_OUTPUT2("=a" (__ret), "+m" (pcp1), \ 472: "+m" (pcp2), "+d" (__o2)), \ 473: "b" (__n1), "c" (__n2), "a" (__o1) : "rsi"); \ 474: __ret; \ 475: }) 476: 477: #define __this_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double 478: #define this_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double 479: 480: #endif 481: 482: /* This is not atomic against other CPUs -- CPU preemption needs to be off */ 483: #define x86_test_and_clear_bit_percpu(bit, var) \ 484: ({ \ 485: int old__; \ 486: asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \ 487: : "=r" (old__), "+m" (var) \ 488: : "dIr" (bit)); \ 489: old__; \ 490: }) 491: 492: static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr, 493: const unsigned long __percpu *addr) 494: { 495: unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG; 496: 497: #ifdef CONFIG_X86_64 498: return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_8(*a)) != 0; 499: #else 500: return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_4(*a)) != 0; 501: #endif 502: } 503: 504: static inline int x86_this_cpu_variable_test_bit(int nr, 505: const unsigned long __percpu *addr) 506: { 507: int oldbit; 508: 509: asm volatile("bt "__percpu_arg(2)",%1\n\t" 510: "sbb %0,%0" 511: : "=r" (oldbit) 512: : "m" (*(unsigned long *)addr), "Ir" (nr)); 513: 514: return oldbit; 515: } 516: 517: #define x86_this_cpu_test_bit(nr, addr) \ 518: (__builtin_constant_p((nr)) \ 519: ? x86_this_cpu_constant_test_bit((nr), (addr)) \ 520: : x86_this_cpu_variable_test_bit((nr), (addr))) 521: 522: 523: #include <asm-generic/percpu.h> 524: 525: /* We can use this directly for local CPU (faster). */ 526: DECLARE_PER_CPU(unsigned long, this_cpu_off); 527: 528: #endif /* !__ASSEMBLY__ */ 529: 530: #ifdef CONFIG_SMP 531: 532: /* 533: * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu 534: * variables that are initialized and accessed before there are per_cpu 535: * areas allocated. 536: */ 537: 538: #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 539: DEFINE_PER_CPU(_type, _name) = _initvalue; \ 540: __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ 541: { [0 ... NR_CPUS-1] = _initvalue }; \ 542: __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map 543: 544: #define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \ 545: DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue; \ 546: __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ 547: { [0 ... NR_CPUS-1] = _initvalue }; \ 548: __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map 549: 550: #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 551: EXPORT_PER_CPU_SYMBOL(_name) 552: 553: #define DECLARE_EARLY_PER_CPU(_type, _name) \ 554: DECLARE_PER_CPU(_type, _name); \ 555: extern __typeof__(_type) *_name##_early_ptr; \ 556: extern __typeof__(_type) _name##_early_map[] 557: 558: #define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \ 559: DECLARE_PER_CPU_READ_MOSTLY(_type, _name); \ 560: extern __typeof__(_type) *_name##_early_ptr; \ 561: extern __typeof__(_type) _name##_early_map[] 562: 563: #define early_per_cpu_ptr(_name) (_name##_early_ptr) 564: #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx]) 565: #define early_per_cpu(_name, _cpu) \ 566: *(early_per_cpu_ptr(_name) ? \ 567: &early_per_cpu_ptr(_name)[_cpu] : \ 568: &per_cpu(_name, _cpu)) 569: 570: #else /* !CONFIG_SMP */ 571: #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 572: DEFINE_PER_CPU(_type, _name) = _initvalue 573: 574: #define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \ 575: DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue 576: 577: #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 578: EXPORT_PER_CPU_SYMBOL(_name) 579: 580: #define DECLARE_EARLY_PER_CPU(_type, _name) \ 581: DECLARE_PER_CPU(_type, _name) 582: 583: #define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \ 584: DECLARE_PER_CPU_READ_MOSTLY(_type, _name) 585: 586: #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu) 587: #define early_per_cpu_ptr(_name) NULL 588: /* no early_per_cpu_map() */ 589: 590: #endif /* !CONFIG_SMP */ 591: 592: #endif /* _ASM_X86_PERCPU_H */ 593: